Solid-state image pickup device, and manufacturing method thereof

ABSTRACT

The present invention aims to provide a solid-state imaging apparatus that realizes less leakage current, high image quality and low noise during the driving operation, and manufacturing method for the same.  
     A MOS type imaging apparatus  1  includes an imaging region  10  and a driving region  20  both formed on a p-type silicon substrate (hereinafter called an “Si substrate”)  31.    
     The imaging region  10  includes six pixels  11  to  16  disposed in a shape of a matrix having 2 rows and 3 columns. The driving region  20  includes a timing generation circuit  21 , a vertical shift resistor  22 , a horizontal shift resistor  23 , a pixel selection circuit  24 , and so on.  
     All transistors included in the pixels  11  to  16  in the imaging region and the circuits  21  to  24  in the driving circuit region  20  are of n-channel MOS type.

TECHNICAL FIELD

The present invention relates to a solid-state imaging apparatus usedfor a digital camera and so on, and a manufacturing method for the same.

BACKGROUND ART

Among solid-state imaging apparatuses, MOS (Metal Oxide Semiconductor)type imaging apparatuses include pixels two-dimensionally disposed on asubstrate, each of which subjects input light to photoelectricconversion performed by a photodiode disposed in the pixel to generatesignal charge, and amplifies the generated signal charge by anamplification circuit placed in the pixel. The amplified signal chargeis to be read out from the pixel. Such MOS type imaging apparatuses canbe driven with a low voltage and low power consumption. Also, an imagingregion and a drive circuit region that drives the imaging region can berealized as one chip. In other words, they can be formed on onesubstrate. Therefore, the MOS type imaging apparatuses are attractingconsiderable attention as image input devices of portable appliances.

Conventional MOS type imaging apparatuses are structured in such amanner that the imaging region and the drive circuit region are formedon one silicon substrate (hereinafter called the “Si substrate”) basedon CMOS (Complementary Metal Oxide Semiconductor) processing technology.In the CMOS processing technology, apparatuses and processes have beendesigned and developed with the main aim of making the driving speedfaster.

The imaging region includes a plurality of pixels that are disposed onthe Si substrate two-dimensionally (e.g. in a shape of a matrix). Eachpixel includes a photodiode unit for converting received light to signalcharge, a MOS type transistor for performing a switching function, and aMOS type transistor for amplifying signals.

The signal charge generated in the photodiode unit by the photoelectricconversion is amplified in each pixel by a switching operation based oninstruction signals received from a vertical shift resistor and ahorizontal shift resistor, which are included in a drive circuit regiondescribed later. Then the amplified signal is to be read out from eachpixel.

Every MOS type transistor included in the imaging region is of ann-channel MOS type.

The drive circuit region includes four main circuits, namely a timinggenerator circuit, a vertical shift resistor, a horizontal shiftresistor, and a pixel selection circuit. Every MOS type transistorincluded in the drive circuit region has a CMOS structure, which is acombination of an n-channel MOS type and a p-channel MOS type.

The n-channel MOS type transistors in the imaging region andthen-channel MOS type transistors in the drive circuit region usuallyhave the same structure.

The following describes the circuit structure of the horizontal shiftresistor, with reference to FIG. 10. Generally, the horizontal shiftresistor has several stages. The number of the stages is in accordancewith the number of pixel lines. FIG. 10 shows only the 1^(st) stage ofthe horizontal shift resistor.

As FIG. 10 shows, the 1^(st) stage 50 of the horizontal shift resistorincludes four switches 51, 54, 55 and 58, and four inverters 52, 53, 56and 57. Each of the switches 51, 54, 55 and 58, and each of theinverters 52, 53, 56 and 57 includes a pair of an n-channel MOS typetransistor and a p-channel MOS type transistor.

The inverters 52 and 53 are connected in series with each other. Thepair of inverters 52 and 53 is connected in parallel with the switch 54.The switch 51 is connected in series with the group of the inverters 52and 53 and the switch 54 that are in the above-described relation.

The switches 55 and 58 and the inverters 56 and 57 have the samerelation as described above.

The 1^(st) stage 50 of the horizontal shift resistor, having such astructure, starts the driving operation when being applied a start pulseVST by the switch 51, and outputs an operation pulse of the 1^(st) stageto the pixel selection circuit when being applied a clock pulse CK1 andits inversion pulse CK2 twice for each. Then, the horizontal shiftresistor outputs operation pulses of the 2^(nd) and 3^(rd) stagessequentially.

The following describes the device structure of a transistor (CMOS type)in the 1^(st) stage of the horizontal shift resistor, with reference toFIG. 11. FIG. 11 is a cross-sectional view showing the device structureof the above-described switches 51, 54, 55 and 58, or inverters 52, 53,56 and 57.

As FIG. 11 shows, an n-well 62 and a p-well 63 are formed underneath thesurface of the Si substrate 61 with an interval.

A gate insulator 64 is formed on the surfaces of the Si substrate 61 soas to cover the n-well 62 and the p-well 63. Gate electrodes 67 and 70are formed on the surface of the gate insulator 64 so as to be on asubstantially center portions of the wells respectively.

Source regions 65 and 69, and drain regions 66 and 68 are formedunderneath the boundary portion between the gate insulator 64 and thewells 62 and 63.

In such a manner, a p-channel MOS type transistor is formed on the Sisubstrate 61 from three electrodes, namely the gate electrode 67, thesource region 65 and the drain region 66. Also, an n-channel MOS typetransistor is formed on the Si substrate 61 from three electrodes,namely the gate electrode 70, the source region 68, and the drain region69.

The MOS type imaging apparatus having the CMOS structure is formedthrough following steps 1 to 15 aimed at the Si substrate 61.

-   1. Form a resist for forming the n-well 62.-   2. Form the n-well 62.-   3. Remove the resist for forming the n-well 62.-   4. Form a resist for forming the p-well 63.-   5. Form the p-well 63.-   6. Remove the resist for forming the p-well 63.-   7. Form the gate insulator 64.-   8. Form the gate electrodes 67 and 70.-   9. Form a resist for forming the source region 65/the drain region    66 of n-channel MOS type.-   10. Form the source region 65/the drain region 66 of n-channel MOS    type.-   11. Remove the resist for forming the source region 65/the drain    region 66 of n-channel MOS type.-   12. Form a resist for forming the source region 68/the drain region    69, which are of p-channel MOS type.-   13. Form the source region 68/the drain region 69 of p-channel MOS    type.-   14. Remove the resist for forming the source region 68/the drain    region 69 of p-channel MOS type.-   15. Form the photodiode unit.

However, the conventional MOS type imaging apparatuses manufacturedbased on such a CMOS processing technology might suffer, in the imagingregion, leakage current in the photodiode unit and characteristicdeterioration in the amplification circuit during the driving operation,which become causes of a noise. When a noise is caused in the imagingregion, it is amplified and output with the signal charge, resulting indeterioration of the image quality.

DISCLOSURE OF THE INVENTION

In view of the above problem, the present invention aims to provide asolid-state imaging apparatus that realizes less leakage current, highimage quality and low noise during the driving operation, andmanufacturing method for the same.

The object can be achieved by a solid-state imaging apparatus thatincludes an imaging region and a drive circuit region both formed on onesemiconductor substrate, the imaging region including an active-typeunit pixel in which a photodiode unit generates signal charge byphotoelectric conversion and an amplification unit amplifies the signalcharge, the drive circuit region being for driving the photodiode unitand the amplification unit, the imaging region and the drive circuitregion including one or more transistors respectively, wherein thetransistors in the imaging region and the drive circuit region have asame channel polarity.

In the stated solid-state imaging apparatus, all the transistorsincluded in the imaging region and the drive circuit region have thesame channel polarity. Therefore, as to the stated apparatus, the numberof processes required for forming all the transistors in both regions isonly approximately a half the number of processes required formanufacturing the conventional solid-state imaging apparatus with use ofthe CMOS processing technology. This means that the imaging regionsuffers less damage during the process for forming the transistors.

In other words, the stated solid-state imaging apparatus has anadvantage that it suffers less noise in the amplification unit and lessleakage current in the photodiode unit, and therefore suffers lessdeterioration of the image quality caused by the noise and the leakagecurrent.

Note that the “active-type unit pixel” means a pixel that is formed witha photodiode unit for subjecting the input light, which is input to anarea corresponding to a unit pixel, to the photoelectric conversion, andan amplification unit for amplifying the converted signal.

For realizing a high-speed driving of the apparatus, it is preferablethat the transistors are of an n-channel MOS type.

For reducing the power consumption, it is preferable that the drivecircuit region includes a dynamic circuit that includes a capacitor foraccumulating electric charge and a transistor for performing a switchingfunction.

Usually, a plurality of active-type unit pixels are formed in theimaging region in the solid-state imaging apparatus. Methods, such asscanning method, a random access method, an edge detection method, areused as for reading signal charge from the plurality of the active-typeunit pixels. In particular, for performing the scanning method torealize high-speed driving, it is preferable that the imaging regionincludes a plurality of the active-type unit pixels, and the drivecircuit region includes a pixel selection circuit for selecting oneactive-type unit pixel from the plurality of the active-type unit pixelsand a shift resistor circuit for outputting a selection instructionsignal to the pixel selection circuit.

For reducing the power consumption, it is preferable that the imagingregion includes a transistor for performing a switching function basedon a signal received from the drive circuit region, and the signalcharge is output to the amplification unit while the transistor is ON.

In a case where the gate length of the transistors is as minute as 0.6μm or even less, the conventional CMOS processing technology might causean increase of the leakage current in the photodiode unit and anincrease of the noise in the amplification unit during the drivingoperation. This is because the short channel effect is accelerated asthe number of heating processes increases, and the amplification unit orthe photodiode unit suffers damage when the resists are removed.

On the other hand, when the transistors have the same channel polarityas in the solid-state imaging apparatus of the present invention, theincrease of leakage current during the driving operation is to besuppressed, because the number of heating processes and the number ofprocesses for removing the resists are reduced in the present invention.Therefore, it is advantageous when the transistor is of a MOS type, ofwhich a gate length is equal to or less than 0.6 μm (a design rule forthe value of the gate length defined to be equal to or less than 0.6μm).

In the conventional solid-state imaging apparatus, the gate electrode ofthe transistor is formed on the insulator film covering thesemiconductor substrate. When the gate insulator is a thin film having athickness which is not more than 20 (nm), the leakage current veryfrequently occurs between the gate insulator film and the semiconductorsubstrate. However, if the transistors have the same channel polarity asin the solid-state imaging apparatus of the present invention, lessleakage current occurs even when the solid-state imaging apparatusincludes such a thin gate insulator.

Also, the leakage current can be reduced when the transistor is of a MOStype, of which a film thickness of a gate insulator is in a range from 1nm to 20 nm.

Such solid-state imaging apparatus can be built into a camera and so on,as an input image sensor, which can gain high-quality images.

The manufacturing method for the solid-state imaging apparatus of thepresent invention comprises steps of: forming, on a semiconductorsubstrate, an imaging region including a photodiode unit for convertinginput light into signal charge and an amplification unit for amplifyingthe signal charge; and forming, on the semiconductor substrate, a drivecircuit region for driving the imaging region, wherein MOS typetransistors having a same channel polarity are formed in both steps forforming the imaging region and the drive circuit region respectively.

In this manufacturing method, all the transistors included in theimaging region and the drive circuit region can be formed by only oneprocess, which is the process for forming n-channel MOS type transistorsor the process for forming p-channel MOS type transistors. This meansthat the photodiode unit, the amplification unit and so on, which areincluded in the imaging region, suffer less damage during themanufacturing process. Therefore, the solid-state imaging apparatusmanufactured by the stated manufacturing method suffers less damage inthe imaging region during the manufacturing process, and can reduce thenoise due to the leakage current in the photodiode unit and thecharacteristic deterioration in the amplification unit caused by thedamage.

In other words, the stated manufacturing method can manufacture asolid-state imaging apparatus with high quality images and less noiseduring the driving operation that is capable of reducing the damage onthe photodiode unit and the amplification unit, which is a cause of theleakage current in the photodiode unit and the characteristicdeterioration in the amplification unit.

For realizing high-speed driving of the solid-state imaging apparatus,it is preferable in the stated manufacturing process for the solid-stateimaging apparatus that the MOS type transistors formed in the both stepsare of n-channel MOS type.

The stated manufacturing method can reduce the noise by suppressing theleakage current which occurs during the driving operation even when agate length of each MOS type transistor is equal to or less than 0.6 μm(a design rule for the value of the gate length defined to be equal toor less than 0.6 μm).

Also, the stated manufacturing method is advantageous especially when afilm thickness of a gate insulator in each MOS type transistor is in arange from 1 nm to 20 nm, because it can reduce the leakage currentwhich occurs during the driving operation, by forming the MOS typetransistors so as to have the same channel polarity.

Further, the stated manufacturing method is advantageous especially whenan insulator that has a film thickness in a range from 1 nm to 20 nm andfunctions as a capacitor is formed between a gate electrode of each MOStype transistor and the semiconductor substrate, because it can reducethe leakage current which occurs during the driving operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a MOS type imaging apparatus pertaining to theembodiment of the present invention;

FIG. 2 is a circuit diagram of a pixel 11 in an imaging region 10;

FIG. 3 is a circuit diagram of a horizontal shift resistor 23;

FIG. 4 is an operation timing chart showing an operation of a horizontalshift resistor 23;

FIG. 5 is a cross-sectional view showing a device structure of atransistor in a horizontal shift resistor 23;

FIG. 6 is a manufacturing process chart of an n-channel MOS typetransistor;

FIG. 7 is a manufacturing process chart of an n-channel MOS typetransistor;

FIG. 8 is a comparative characteristic diagram showing a relationbetween a conductive type of a transistor and the number of leakageelectrons in a photodiode;

FIG. 9 is a comparative characteristic diagram showing a relationbetween a conductive type of a transistor and an S/N ratio in anamplifier included in a pixel;

FIG. 10 shows a circuit diagram of a conventional horizontal shiftresistor; and

FIG. 11 is a cross-sectional view showing a device structure of atransistor included in a conventional horizontal sift resistor.

BEST MODE FOR CARRYING OUT THE INVENTION

The following describes a MOS type imaging apparatus which is anembodiment of the present invention, with reference to FIG. 1 to FIG. 3.FIG. 1 is a plan view (a block diagram) showing an overall structure ofa MOS type imaging apparatus 1 as an image input device used for adigital camera pertaining to this embodiment. FIG. 2 is a circuitdiagram of a circuit 11 in a region corresponding to an active-type unitpixel of the MOS type imaging apparatus 1. (A circuit in a regioncorresponding to an active-type unit pixel is hereinafter simply calleda “pixel”.) FIG. 3 is a circuit diagram of a horizontal shift resistor23.

As FIG. 1 shows, the MOS type imaging apparatus 1 includes an imagingregion 10 and a drive circuit region 20 formed on a p-type siliconsubstrate (hereinafter called an “Si substrate”) 31. Circuits includedin the imaging region 10 and in the drive circuit region 20 areelectrically connected with each other with use of a wiring patternformed on the Si substrate 31.

In FIG. 1, circuits included in the regions 10 and 20 are shown asblocks. In practice, however, functional device units included in theregions 10 and 20 are densely formed on the Si substrate 31.

The imaging region 10 includes six pixels 11 to 16 disposed in a shapeof a matrix having 2 rows and 3 columns. The drive circuit region 20includes a timing generator circuit 21, a vertical shift resistor 22, ahorizontal shift resistor 23, a pixel selection circuit 24, and so on.

Among these, the vertical shift resistor 22 and the horizontal shiftresistor 23 are dynamic circuits. They sequentially output drive pulses(switching pulses) to the pixels 11 to 16 or to the pixel selectioncircuit 24 according to a signal received from the timing generatorcircuit 21.

Also, the pixel selection circuit 24 includes three switching devices(not shown in figures), namely one for pixels 11 and 12, one for pixels13 and 14, and one for 15 and 16. They are sequentially turned on byreceiving pulses from the horizontal shift resistor 23.

The six pixels 11 to 16 in the imaging region 10 are active-type unitpixels, each having an amplification unit. The signal charge generatedby the photoelectric conversion is read from a pixel at a position wherea row selected by the vertical shift resistor 22 intersects with acolumn whose pixel selection circuit 24 is turned on.

The timing generator circuit 21 is a circuit for applying a power supplyvoltage, a timing pulse, and so on to the above-described vertical shiftresistor 22 and the horizontal shift resistor 22.

Circuit Structure of Each Pixel in the Imaging Region 10

The six pixels 11 to 16 are active-type unit pixels, and have the samecircuit structure. The following describes the circuit structure of apixel, with reference to FIG. 2, taking the pixel 11 as an example.

As FIG. 2 shows, the pixel 11 includes a photodiode unit 111 and fourtransistors (a transfer transistor 112, a reset transistor 113, anamplification transistor 114, and a selection transistor 115) and so on,formed on the Si substrate 31. Among these, all the four transistors areof n-channel MOS type.

As FIG. 2 shows, the photodiode unit 111 is a device unit having aphotoelectric conversion function, which is for generating signal chargein proportion to the intensity of input light. One end of the photodiodeunit 111 is earthed and the other end is connected with the sourceregion of the transfer transistor 112.

The transfer transistor 112 is a device unit for transferring signalcharge generated by the photodiode unit 111 to a drain region of thetransfer transistor 112 itself. The drain region functions as adetection unit. A gate electrode of the amplification transistor 114 anda source region of the reset transistor 113 are connected with the drainregion.

The reset transistor 113 is a device unit for resetting the signalcharge accumulated in the drain region of the transfer transistor 112 ina predetermined cycle. The drain region of the reset transistor 113 isconnected with the power supply voltage VDD.

The amplification transistor 114 is a device unit for outputting thesignal charge accumulated in the drain region of the transfer transistor112 when the selection transistor 115 is turned on according to signalsreceived from the vertical shift resistor 22 and so on. The drain regionof the amplification transistor 114 is connected with the power supplyvoltage VDD, and the source region of the amplification transistor 114is connected with the drain region of the selection transistor 115.

The source region of the selection transistor 115 is connected with thepixel selection circuit 24.

The gate electrode of the transfer transistor 112, the gate electrode ofthe reset transistor 113, and the gate electrode of the selectiontransistor 115 are respectively connected with the three signal linescoming from the vertical shift resistor 113.

Among four transistors 112 to 115, the amplification transistor 114performs a signal amplification function for the signal charge in thepixel 11, and the other transistors 112, 113 and 115 perform a switchingfunction.

In the pixel 11 having above-described circuit structure, the signalcharge generated by the photodiode unit 111 with use of thephotoelectric conversion is accumulated in the photodiode unit 111. Theaccumulated signal charge in the photodiode unit 111 is to betransferred to the drain region (detection unit) of the transfertransistor 112, and to be output to the gate electrode of theamplification transistor 114, when the transfer transistor 112 is turnedon based on instruction signals received from the vertical shiftresistor 22.

Receiving the signal charge, the amplification transistor 114 amplifiesthe received signal charge.

The selection transistor 115 performs ON/OFF operations based on theinstruction signals received from the vertical shift resistor 22.

The reset transistor 113 eliminates the signal charge accumulated in thedetection unit in a predetermined cycle to reset the accumulation statusof the signal charge in the detection unit.

In the imaging region 10 of the MOS type imaging apparatus 1, each ofthe pixels 11 to 16 accumulates the signal charge generated by thephotoelectric conversion. In one of these pixels, which is selected bythe selection transistor in each pixel and the pixel selection circuit23 based on the instruction signals received from the vertical shiftresistor 22 and the horizontal resistor 23, the signal charge isamplified and output.

Circuit Structure of the Horizontal Shift Resistor 23

Among circuits 21 to 24 included in the drive circuit region 20, thefollowing describes the circuit structure of the horizontal shiftresistor 23, with reference to FIG. 3.

The horizontal shift resistor 23 shown in FIG. 3 is different from theconventional horizontal shift resistor (1^(st) stage) 50 shown in FIG.10 in that all the transistors are of n-channel MOS type.

As FIG. 3 shows, the horizontal shift resistor 23 includes three stages,namely the 1^(st) stage 231, the 2^(nd) stage 232, and the 3^(rd) stage233, so that the number of the stages corresponds to the number ofcolumns of pixels 11 to 16 in the imaging region. The 1^(st) stage 231,the 2^(nd) stage 232, and the 3^(rd) stage 233 have the same circuitstructure. Therefore, the following describes only the circuit structureof the 1^(st) stage 231 as an example.

As FIG. 3 shows, the 1^(st) stage 231 of the horizontal shift resistor23 includes four transistors 2311, 2312, 2316 and 2317, and a bootstrapcapacitor 2313 for bootstrapping. Among these, four transistors 2311,2312, 2316 and 2317 are all n-channel MOS type transistors just as thefour transistors 112 to 115 included in the above-described imagingregion 10.

The charging transistor 2311 is an enhancement-mode n-channel MOS typedevice unit which charges the bootstrap capacitor 2313. The gateelectrode of the charging transistor 2311 is connected with a signalline for the start pulse VST. The drain region of the chargingtransistor 2311 is connected with the power supply voltage VDD, and thesource region of the charging transistor is connected with one end (theplus terminal) of the bootstrap capacitor 2313. Here, the start pulseVST and the power apply voltage VDD are applied by the timing generatorcircuit 21. A drive pulse V1, which is described later, is applied bythe timing generator circuit 21 as well.

The source region of the charging transistor 2311 is connected with anode 2315 and a drain region of a discharge transistor 2316. The node2315 is connected with a gate electrode of an output transistor 2312.

As to the output transistor 2312, the gate is connected with the sourceregion of the charge transistor 2311 via the node 2315 as describedabove, the drain region is connected with a signal line for the drivepulse V1, and the source is connected with the other end (the minusterminal) of the bootstrap capacitor 2313. The source region of theoutput transistor 2312 is connected with the drain region of thedischarge transistor 2317 as well.

An output node 2314 is disposed between the minus terminal of thebootstrap capacitor 2313 and the source region of the output transistor2312, and connected with the imaging region 10.

Source regions of two discharge transistor 2316 and 2317 are earthedrespectively, and the gate electrodes of them are connected with anoutput node 2324 of the 2^(nd) stage 232.

The drain region of the output transistor 2322 included in the 2^(nd)stage 232 is connected with a signal line for a drive pulse V2.

The circuit structure of the 2^(nd) stage 232 is the same as the 1^(st)stage 231 except the above-described components.

Also, the circuit structure of the 3^(rd) stage 233 is the same as theother stages except that the drain region of the output transistor 2332is connected with the signal line for the drive pulse V1.

As described above, the shift resistor 23, whose transistor is formedwith only n-channel MOS type, includes four transistors and onecapacitor for each stage. The above-described conventional horizontalshift resistor having the conventional CMOS type structure, which isshown in FIG. 11, includes 16 transistors for each stage. Meanwhile, thehorizontal shift resistor 23 includes fewer functional device units(transistors and a capacitor), namely only five in total.

Therefore, the horizontal shift resistor 23 can gain the same or evenhigher drive speed than the high drive speed of the horizontal shiftresistor of CMOS type shown in FIG. 10. This is realized by designing acircuit in such a manner that the number of necessary functional devicesis to be reduced.

Drive Operation of the Horizontal Shift Resistor 23

The following describes the drive operation of the horizontal shiftresistor 23 having the above-described circuit structure, with referenceto FIG. 4. FIG. 4 is a drive timing chart of the horizontal shiftresistor 23.

As FIG. 4 shows, in the horizontal resistor 23, the charging transistor2311 is turned on when a start pulse VST (voltage 5(V)) is applied tothe gate electrode of the charging transistor 2311 at a time t0. Whenthe charging transistor 2311 is turned on, a voltage begins to beapplied to the gate electrode of the output transistor 2312, and theoutput transistor 2312 is turned on as well. Here, the drive pulse V1,which is input to the drain region of the output transistor 2312, is aground potential, and a potential difference, which is the same as thepower supply voltage VDD, occurs between the both ends of the bootstrapcapacitor 2313. As a result, the bootstrap capacitor 2313 is to becharged until it gains the same voltages as the power supply voltage VDD(3(V)).

Next, when the drive pulse V1 rises up to 3(V) and is input to the drainregion of the output transistor 2312 at a time t1, a high voltage HB1(6(V)), which is the addition of the voltage 3(V) of the drive pulse V1and the voltage 3(V) at the both ends of the bootstrap capacitor 2313,is applied to the gate electrode of the output transistor 2312, as apulse VN11. Accordingly, the output node 2314 outputs an operation pulseVN12 having an amplitude of 3(V) as an output pulse Out1 to theswitching device units corresponding to the pixels 11 and 12 in the1^(st) column for the pixel selection circuit 24.

Also, the pulse Vn11 at the high voltage HB1 is applied to the gateelectrode of the charging transistor 2321 included in the 2^(nd) stage232. As a result, the charging transistor 2321 is turned on. Then, whenthe charging transistor 2321 in the 2^(nd) stage 232 is turned on, theoutput transistor 2322 is turned out as well. The drive pulse V2 is aground potential. Therefore, the bootstrap capacitor 2323 is chargeduntil it gains the same voltages as the power supply voltage VDD (3(V)).

When the drive pulse V2 rises up to 3(V) and is input to the drainregion of the output transistor 2322 at a time t2, a high voltage HB2(6(V)), which is the addition of the voltage 3(V) of the drive pulse V2and the voltage 3(V) at the both ends of the bootstrap capacitor 2323,is applied to the gate electrode of the output transistor 2322, as apulse VN21. Accordingly, the output node 2324 outputs an operation pulseVN22 having an amplitude of 3(V) as an output pulse Out2 to theswitching device units corresponding to the pixels 13 and 14 in the2^(nd) column for the pixel selection circuit 24.

Also, the pulse VN21 at the high voltage HB2 is applied to the gateelectrode of the charging transistor 2331 included in the 3^(rd) stage233 for performing the same drive operation as described above. At atime t3, the output node 2334 outputs an operation pulse VN32 as anoutput pulse Out3 having an amplitude of 3(V) to the switching deviceunits corresponding to the pixels 15 and 16 in the 3^(rd) column for thepixel selection circuit 24.

Also, the operation pulse VN22 from the output node 2324 in the 2^(nd)stage 232 turns on the discharge transistors 2316 and 2317 at the sametime. Then, the charged content in the bootstrap capacitor 2313 is to bedischarged.

Note that the discharge of the bootstrap capacitor 2313 may be performedwith the drive pulse V2.

As described above, the horizontal shift resistor 23 whose transistorsare all n-channel MOS type has fewer transistors than the horizontalshift resistor 50 shown in FIG. 11 formed by the conventional CMOSprocess, but can generate and sequentially output the output pulses Out1to 3 which are free from a voltage drop.

Therefore, the horizontal shift resistor 23 provides an equalperformance to the horizontal shift resistor 50, including the drivespeed.

Note that other than the horizontal shift resistor 23, the drive circuitregion 20 includes the timing generator circuit 21, the vertical shiftresistor 22, and the pixel selection circuit 24, and so on, and they canprovide an equal performance to the counterparts that are designed andmanufactured based on the CMOS process technology.

The Device Structure of the Transistor in the MOS Type Imaging Apparatus1

In the MOS type imaging apparatus 1 pertaining to the embodiment of thepresent invention is characterized in that all the transistors includedin both the imaging region 10 and the drive circuit region 20 aren-channel MOS type transistors. The following describes the devicestructure of the transistors with reference to FIG. 5.

As FIG. 5 shows, a gate insulator 32 made of SiO₂, which is insulative,is formed on the surface of an Si substrate 31. The film thickness ofthe gate insulator 32 is in a range of 1 (nm) to 20 (nm), for instance.

The Si substrate has the p-type characteristic.

A source region 33 and a drain region 34 are inwardly formed on theboundary portion between the Si substrate 31 and the gate insulator 32with an interval.

A gate electrode 35 made of polysilicon is formed on the area on thesurface of the gate insulator 32, corresponding to the interval betweenthe source region 33 and the drain region 34.

As FIG. 5 shows, an n-channel MOS type transistor is formed on the Sisubstrate 31 from three electrodes, namely the gate electrode 35, thesource region 33 and the drain region 34, and the surface part of the Sisubstrate just under the gate electrode 35 becoming a channel.

A method for Forming the Transistor

The following describes a method for forming the transistor included inthe MOS type imaging apparatus 1, with reference to FIG. 6 and FIG. 7.

By processing the Si substrate shown in FIG. 6A in oxidizing atmosphere,the Si substrate shown in FIG. 6B made of SiO₂ is obtained, on which thegate insulator 32 as an insulator is formed.

By depositing polysilicon (polycrystalline silicon) in a predeterminedarea on the surface of the gate insulator 32, a gate electrode 35 isformed as shown in FIG. 6. For forming the gate electrode 35, the LPCVDmethod may be used, for instance.

As FIG. 6D shows, resist films 400 are formed with a desired pattern onboth sides of the gate electrode 35 on the gate insulator 32 withpredetermined intervals.

As FIG. 7A shows, the source region 33 and the drain region 34 areformed by ion implantation of arsenic (As) and phosphorous (P) into theSi substrate 31 from the side of surface of the gate insulator 32 and byheat treatment for activation. When performing the ion implantation, aself-aligning method is used, in which the gate electrode 35 alsoperforms a role as resist, and therefore the position of the sourceregion 33 and the drain region 34 can be determined accurately.

Finally, by ashing process performed in oxygen plasma, the resists 400are removed, and the transistor is formed on the Si substrate 31 as FIG.7B shows.

Note that the gate insulator 32 between the gate electrode 35 and the Sisubstrate 31 in the transistor has a function of a capacitor as well.

Advantages of All the Transistors Being n-Channel MOS Type

As a result of research to find the cause of deterioration of imagequality during the driving operation, the inventors discover that amanufacturing method using the above-described CMOS processingtechnology causes damage during the process to region where theamplification unit or the photodiode unit is formed or to be formed, andthe damage affects the image quality during the driving operation.

More specifically, in the above-described manufacturing method, the twosteps for removing the resists, namely steps 3 and 6, damages thesurface of the Si substrate 61 on which the transistor in the imagingregion is to be formed. This damage sometimes causes defects at thebottom parts of the gate electrodes 67 and 70 included in thetransistor. These defects might result in characteristic deterioration,such as an increase of 1/f noise.

Also, after the gate electrodes 67 and 70 are formed in the imagingregion, the two steps for removing resists, namely steps 11 and 14,sometimes damage the gate insulator 64 on the both sides of the gateelectrodes 67 and 70 in the imaging region. When this happens, a leakagecurrent readily occurs between the gate electrodes 67 and 70, the sourceregions 65 and 68, and the drain regions 66 and 69, which lead to anincrease of a noise in the amplification unit. Especially, the leakagecurrent in the amplification unit increases when the gate insulator 32is a thin film of which the thickness is not more than 20 (nm).

Further, the four steps for removing resists, namely steps 3, 6, 11 and14 damages the surface of the Si substrate 61 on which the photodiodeunit is to be formed, and this damage becomes the cause of the leakagecurrent during the driving operation. This leakage current is to beadded to the signal generated by the photoelectric conversion, resultingin the deterioration of the image quality caused by an increase of pixeldefects.

As described above, in the MOS type imaging apparatus manufactured withuse of the conventional manufacturing method, the imaging region suffersdamage during the manufacturing process. This damage causes the leakagecurrent in the photodiode unit and increases the noise in theamplification unit, resulting in the deterioration of the image quality.

In contrast, in the manufacturing method for the MOS type imagingapparatus 1 shown in FIG. 6 and FIG. 7 described above, the resists areremoved only once in the manufacturing process for the transistor.Compared to the above-described conventional manufacturing method, themanufacturing method for the MOS type imaging apparatus does not includethe steps 3 and 6 for removing resists relating to the formation of thewell, because the p-type Si substrate 31 is used. The manufacturingmethod for the MOS type imaging apparatus includes only the step 11 forremoving resists relating to the formation of the source region 33 andthe drain region 34.

Therefore, the manufacturing method pertaining to the embodimentsuppresses the 1/f noise in the amplification unit caused by a defect ata bottom part of the gate electrode 35, a leakage current in theamplification unit caused by damage of the gate insulator 32 on bothsides of the gate electrode 35, and a leakage current in the photodiodeunit caused by a defect of the Si substrate 31 at a bottom part of thephotodiode unit. In particular, the leakage current can be greatlysuppressed when the gate insulator 32 is a thin film of which thethickness is not more than 20 (nm) as well. This shows that the MOS typeimaging apparatus 1, in which all the transistors are formed withn-channel MOS type transistors, has advantages.

In conclusion, the MOS type imaging apparatus 1 with high image qualitycan be manufactured by the manufacturing method pertaining to theembodiment, in which all the transistors in both the imaging region 10and the drive circuit region 20 are formed with n-channel MOS typetransistors. This is because the manufacturing method can suppress thedamage on the imaging region 10 caused during the manufacturing process.

Comparative Experiment

The following is a performance comparison between the MOS type imagingapparatus 1, in which all the transistors in both the imaging region 10and the drive circuit region 20 are formed with n-channel MOS typetransistors, and the conventional CMOS type imaging apparatusmanufactured with CMOS processing technology.

As to the number of the leakage electrons occurred in the photodiodeunit, the leakage electrons occurred in the photodiode unit in a statewithout input light are read into the gate electrode of theamplification transistor (by the transfer transistor) to be detected.FIG. 8 shows the result of the detection.

Assuming that the number of the leakage electrons occurred in thephotodiode unit of the conventional CMOS type imaging apparatus is 1,the number of the leakage electrons occurred in the photodiode unit ofn-channel MOS type imaging apparatus is 0.82, as FIG. 8 shows. That is,the number of the leakage electrons is reduced by 18%.

As to he S/N ratio in the amplification unit (the amplificationtransistor), the S/N ratio is measured in a camera manufactured so as toinclude the solid-state imaging apparatus, with use of an S/N measuringinstrument. FIG. 9 shows the measurement result.

As FIG. 9 shows, the S/N ration in the amplification unit is 57 dB inthe n-channel MOS type imaging apparatus, whereas the S/N ratio is 54 dBin the conventional CMOS type imaging apparatus, which means that then-channel MOS type imaging apparatus has 3 dB advantage.

As described above, the MOS type imaging apparatus 1, in which all thetransistors on the Si substrate 31 are formed with n-channel MOS typetransistors, has advantages of two characteristics over the conventionalCMOS type imaging apparatus, namely the number of the leakage electronsoccurred in the photodiode and the S/N ratio in the amplification unit.This is because the photodiode unit and the amplification transistorsuffer less damage in the manufacturing process.

In conclusion, as the above-described result of the comparison shows,the MOS type imaging apparatus 1 pertaining to the embodiment has acharacteristic that realizes high-quality images, because all thetransistors in both the imaging region 10 and the drive circuit region20 are formed with n-channel MOS type transistors, in which less leakagecurrent occurs in the photodiode unit during the driving operation, andless noise occurs in the amplification transistor.

Supplementary Explanations

Note that the above-described embodiment is an example for explainingthe characteristics and the advantages of the present invention.Therefore, the present invention is not limited to the example exceptthat all the transistors in the apparatus are formed with n-channel MOStype transistors, which is the essential characteristic.

For instance, as to the number of the pixels in the imaging region andthe arrangement of the pixels, the structure of the pixels is notlimited to the above-described structure having 2 rows×3 columns. Also,other circuits may be included in the drive circuit region in additionto the above-described circuits 21 to 24.

Also, the circuit diagrams shown in FIG. 2 and FIG. 3 are examples aswell. Other circuit structures in accordance with the intended use ofthe apparatus may be employed.

Further, a device isolation unit made of a dispersive oxidized film andsoon maybe formed between adjacent transistors. Note, however, that thephotodiode, the amplification transistor and so on should be protectedagainst damage in the process for manufacturing the device isolationunit to prevent the noise which occurs during the driving operation.

In the above-described embodiment, an Si substrate having the p-typecharacteristics is used. However, the Si substrate having p-type wells,which are formed on where those are required, may be used. An SOI(Silicon on Insulator) may be used as well. This is effective inimproving the isolation between the functional portions and between thecircuits.

INDUSTRIAL APPLICABILITY

The solid-state imaging apparatus pertaining to the present inventionand the manufacturing method for the same are effective in realizing asolid-state imaging apparatus with reduced leakage current during thedriving operation and high-quality images.

1. A solid-state imaging apparatus that includes an imaging region and adrive circuit region both formed on one semiconductor substrate, theimaging region including an active-type unit pixel in which a photodiodeunit generates signal charge by photoelectric conversion and anamplification unit amplifies the signal charge, the drive circuit regionbeing for driving the photodiode unit and the amplification unit, theimaging region and the drive circuit region including one or moretransistors respectively, wherein the transistors in the imaging regionand the drive circuit region have a same channel polarity.
 2. Thesolid-state imaging apparatus according to claim 1, wherein thetransistors are of an n-channel MOS type.
 3. The solid-state imagingapparatus according to claim 1, wherein the drive circuit regionincludes a dynamic circuit that includes a capacitor for accumulatingelectric charge and a transistor for performing a switching function. 4.The solid-state imaging apparatus according to claim 3, wherein theimaging region includes a plurality of active-type unit pixels, and thedrive circuit region includes a pixel selection circuit for selectingone active-type unit pixel from the plurality of active-type unit pixelsand a shift resistor circuit for outputting a selection instructionsignal to the pixel selection circuit.
 5. The solid-state imagingapparatus according to claim 1, wherein the imaging region includes atransistor for performing a switching function based on a signalreceived from the drive circuit region, and the signal charge is outputto the amplification unit while the transistor for performing theswitching function is ON.
 6. The solid-state imaging apparatus accordingto claim 1, wherein the transistor is of a MOS type, of which a gatelength is equal to or less than 0.6 μm.
 7. The solid-state imagingapparatus according to claim 1, wherein the transistor is of a MOS type,of which a film thickness of a gate insulator is in a range from 1 nm to20 nm.
 8. The solid-state imaging apparatus according to claim 1,wherein the transistor is of a MOS type, and an insulator that has afilm thickness in a range from 1 nm to 20 nm and functions as acapacitor is formed between a gate electrode of the transistor and thesemiconductor substrate.
 9. A camera that includes the solid-stateimaging apparatus according to claim
 1. 10. A manufacturing method for asolid-state imaging apparatus, comprising steps of: forming, on asemiconductor substrate, an imaging region including a photodiode unitfor converting input light into signal charge and an amplification unitfor amplifying the signal charge; and forming, on the semiconductorsubstrate, a drive circuit region for driving the imaging region,wherein MOS type transistors having a same channel polarity are formedin both steps for forming the imaging region and the drive circuitregion respectively.
 11. The manufacturing method for a solid-stateimaging apparatus according to claim 10, wherein the MOS typetransistors formed in the both steps are of n-channel MOS type.
 12. Themanufacturing method for a solid-state imaging apparatus according toclaim 10, wherein a gate length of each MOS type transistor is equal toor less than 0.6 μm.
 13. The manufacturing method for a solid-stateimaging apparatus according to claim 10, wherein a film thickness of agate insulator in each MOS type transistor is in a range from 1 nm to 20nm.
 14. The manufacturing method for a solid-state imaging apparatusaccording to claim 10, wherein an insulator that has a film thickness ina range from 1 nm to 20 nm and functions as a capacitor is formedbetween a gate electrode of each MOS type transistor and thesemiconductor substrate.